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fsan oc3 symmetric olt transceiver - g983.3 classb - OAT1523S-OLT-V2-B-10 1 / document no: qps-0201-024 rev. draft 0.3 fsan olt oc3 symmetric transceiver g983.3 class b OAT1523S-OLT-V2-B-10 data sheet modification history rev. date originator comment draft0.1 june 12 , 2001 h. okada draft0.2 july 25 , 2001 h. okada mean launched power range, minimum sensitivity, power comsumption draft0.3 june 10 , 2002 h. okada
fsan oc3 symmetric olt transceiver - g983.3 classb - OAT1523S-OLT-V2-B-10 2 / document no: qps-0201-024 rev. draft 0.3 1. general description the OAT1523S-OLT-V2-B-10 is compliant with recommendation itu-t g.983.3 option1 class b for use in atm-pon application s . the OAT1523S-OLT-V2-B-10 is applicable for the optical interface of th e olt function at the central office. these modules have the following functions. (oat1523s-olt1-v2-b-10) -1-fiber bi-directional transmission us in g incorporated wavelength division multiplexer (wdm). -conversion of 155.52 mbps electric signal to 1.49 um optical signal us in g laser diode (e/o conversion). -stabilization of optical output power and waveform with automatic power control (apc) circuit. -transmit failure (tf) detection. -detection of the abnormal increase in laser diode (td) . -optical signal output shut down (ls). -conversion of 155.52 mbps 1.31 um optical signal to electric signal us in g pin-photo diode (o/e conversion). -burst signal reception by automatic threshold control (atc) circuit and burst bit synchronization technique. the specifications are shown on the table 1.1 table 1.1 specifications parameter unit specifications bit rat e m b ps 155.52 transmission mode ? tx: continuous, rx: burst transfer code ? nrz bi-directional transmission ? 1-fibre wdm transmission distance k m 20 laser diod e ? 1.49um dfb-ld p hoto detecto r ? pin-pd operating temperature range c 0 ~ 70 operating humidity % 5 ~ 90 fiber/connector type ? single mode fiber (10/125nm) / pc polished sc connector power supply voltage v +3.3 +/-5% power consumptio n w 1.5 (typ.) , 2.0 (max.) dimension m m 40 60 8.5
fsan oc3 symmetric olt transceiver - g983.3 classb- OAT1523S-OLT-V2-B-10 3 / document no: qps-0201-024 rev. draft 0.3 2. absolute maximum ratings stress in excess of the maximum absolute ratings can cause permanent damage to the module. table 2.1 absolute maximum ratings parameter s ymbol conditions ratings unit power supply voltage vcc 0 to +4.6 v input voltag e v i 0 to vc c v maximum output current io ta = 25 ? 30 m a operating temperatur e t o p 0 t o + 7 0 ? storage temperatur e tst g -40 to +8 5 ? soldering temperature/tim e 250/1 0 c /sec maximum tension of fibe r 5 0 0 g minimum bending radiu s 3 0 m m maximum optical input power ta = 25 ? 0 dbm 3. block diagram pd ld pd ld driver apc d-ff tf 1310nm opt i/o 1310nm/1490nm wdm clk in data in shut in cdr atc pre-amp 1490nm data out clk out sync. loss td cd clock detection cdr reset in atc reset in poc in figu re 3.1 block diagram
fsan oc3 symmetric olt transceiver - g983.3 classb- OAT1523S-OLT-V2-B-10 4 / document no: qps-0201-024 rev. draft 0.3 4. package outline (1) (12) (32) (13) 30.32C0.3 12 - 0 .45 19x1.27 =24.13C0.3 7.775 8.5max (3.39) 13x2.54 = 33.02C0.3 (3.39) (7.8) 20 - 0 .45 40C1 60C1 (top view) 0.8 1.27 (3.1) (4.9) (6.6) (0.4) (3.29) 3.29 (3.6) 33.0 C 0.3 39.6 C 0.3 (38) 1060 +100 -100 (10) 27.9 (4.125) 12.1 fig 4.1 package outline
fsan oc3 symmetric olt transceiver g983.3 classb- OAT1523S-OLT-V2-B-10 5 / document no: qps-0201-024 rev. draft 0.3 5. pin description table 5.1 pin descriptions no. i/o symbol level logic functionality 01 svcc transmitter power supply (+3.3v) 02 gnd ground 03 i sdatap lvpecl data input (pos) 04 i sdata n lvpecl p data input (neg) 05 i sclkp lvpecl clock input (pos) 06 i sclkn lvpecl p clock input (neg) 07 gnd ground 08 i shut lvttl p optical output shut down 09 o cd lvttl p clock down alarm 10 o td lvttl p transmitter degraded alarm 11 o tf lvttl p transmitter failure alarm 12 gnd ground 13 gnd ground 14 o alm lvttl p sync. out alarm 15 gnd ground 16 i poc lvttl n power on clear 17 i brsp lvpecl cdr reset (pos) 18 i brsn lvpecl n cdr reset (neg) 19 gnd ground 20 o rclkp lvpecl clock output (pos) 21 o rclkn lvpecl p clock output (neg) 22 gnd ground 23 o rdatap lvpecl data output (pos) 24 o rdata n lvpecl p data output (neg) 25 gnd ground 26 bvcc power supply for cdr (+3.3v) 27 gnd ground 28 gnd ground 29 i rsn lvpecl atc reset (neg) 30 i rsp lvpecl n atc reset (pos) 31 gnd ground 32 rvcc power supply for atc (+3.3v)
fsan oc3 symmetric olt transceiver g983.3 classb- OAT1523S-OLT-V2-B-10 6 / document no: qps-0201-024 rev. draft 0.3 6. optical and electrical characteristics table 6.1 optical characteristics parameter unit operating wavelength nm tx:1480 ~ 1500 rx:1260 ~ 1360 mask of the transmitter eye diagra m figure 6.1 maximum reflectance of equipment, measured at transmitter wavelength db ? mean launched power range d b m s ol: -0.5 to +2 /eol: -1 to +2 minimum extinction ratio db 10 tolerance to the transmitter incident light power db more than -15 launched optical power w/o input to the transmitter dbm ? maximum spectral width nm 1 (@-20db) side mode suppression ratio db more than 30 jitter transfer ? jitter generation in 1.3khz bandwidth uipp ? maximum reflectance of equipment, measured at receiver wavelength db less than -20 bit error ratio ? less than 10 -10 minimum sensitivity dbm s ol: -33.5/eol: -33.0 minimum overload dbm sol: -7.5/eol: -8.0 consecutive identical digit immunity ? more than 72 jitter tolerance ?? tolerance to the reflected optical power db more than- 10 table 6.2 electrical characteristics parameter unit min typ max pecl input high voltag e v cc -1.1 7 v cc -0.88 pecl input low voltag e v cc -1.8 1 v cc -1.47 pecl output high voltag e v cc -1.0 2 v cc -0.88 pecl output low voltag e v cc -1.8 1 v cc -1.62 lvttl input high voltag e 2 . 0 v cc +0.3 lvttl input low voltage -0.3 0.8 lvttl output high voltage 2.4 vcc lvttl output low voltage v 0 0.4 clock input duty % 40 50 60 clock/data output timin g figure 6.2 clock/data output timin g figure 6.3 reset input timin g figure 6.4 power on clear input timin g figure 6.5 tracking alarm output timin g figure 6.6 required preamble pattern 10101010
fsan oc3 symmetric olt transceiver g983.3 classb- OAT1523S-OLT-V2-B-10 7 / document no: qps-0201-024 rev. draft 0.3 figure 6.1 eye pattern mask this timing is based on the data cross point. figure 6.2 clock/data input timing 1+ y 1 amplitude ui y 1 0 0.5 1 x 1 0 -y 1 y 2 x 2 x 3 x 4 1 0.25/0.75 0.4/0.6 0.20/0.80 1 1 y 1 2 4 0.15/0.85 0.35/0.65 0.20/0.80 x 1 /x 4 x 2 /x 3 y 1 /y 2 1 / 4 / 3 / mean level of logical ?g 1 ?h mean level of logical ?g 0 ?h 1+ y 1 amplitude ui y 1 0 0.5 1 x 1 0 -y 1 y 2 x 2 x 3 x 4 1 0.25/0.75 0.4/0.6 0.20/0.80 1 1 y 1 2 4 0.15/0.85 0.35/0.65 0.20/0.80 x 1 /x 4 x 2 /x 3 y 1 /y 2 1 / 4 / 3 / x 1 /x 4 x 2 /x 3 y 1 /y 2 1 / 4 / 3 / mean level of logical ?g 1 ?h mean level of logical ?g 0 ?h t setup > 1.2ns , t hold > 1.2ns data input clock input t setup t hold t setup > 1.2ns , t hold > 1.2ns data input clock input t setup t hold
fsan oc3 symmetric olt transceiver g983.3 classb- OAT1523S-OLT-V2-B-10 8 / document no: qps-0201-024 rev. draft 0.3 this timing is based on the data cross point. figure 6.3 clock/data output timing figure 6.4 reset input timing t rpw1 t rpw2 atc reset input cdr reset input data output preceding cell preamble of the following cell t3 t4 t5 t1 t2 t rpw1 > 2 bi t t rpw2 = 2 b i t t3 < 26.5bit t 4 >30. 5 b i t t1 < 28.5 bit t 2 > 30. 5 b i t t5 > 0 nsec t rpw1 t rpw2 atc reset input cdr reset input data output t rpw1 t rpw2 atc reset input cdr reset input data output preceding cell preamble of the following cell t3 t4 t5 t1 t2 t rpw1 >2 bit t rpw2 = 2 bit t3 < 26.5bit t4 >30.5 bit t1 < 28.5bit t2 >30.5 bit t5 >0 nsec t rpw1 >2 bit t rpw2 = 2 bit t3 < 26.5bit t4 >30.5 bit t1 < 28.5bit t2 >30.5 bit t5 >0 nsec 0.7ns < dt < 2.0ns data output clock output dt 0.7ns < dt < 2.0ns data output clock output dt
fsan oc3 symmetric olt transceiver g983.3 classb- OAT1523S-OLT-V2-B-10 9 / document no: qps-0201-024 rev. draft 0.3 figure 6.5 power on clear input timing n ote: assertion of tracking alarm does not necessarily represent recovered data error or loss of synchronization. figure 6.6 sync. out alarm reset timing poc power on reset tpw tpw > 10usec poc power on reset tpw tpw > 10usec power (vccr) cdr reset input data input tracking alarm assert cell #1 maximum trackable phase 0.28ui tracking alarm establishment of the synchronization data with phase -variation larger/almost -larger than tracking range. dont care cell #2 tracking range 0.28ui minimum trackable phase out of range out of range tracking alarm assert tracking alarm negate (b) phase condition (a) timing chart power (vccr) cdr reset input data input power (vccr) cdr reset input data input tracking alarm assert cell #1 tracking alarm assert cell #1 maximum trackable phase 0.28ui tracking alarm establishment of the synchronization data with phase -variation larger/almost -larger than tracking range. dont care cell #2 tracking range 0.28ui minimum trackable phase out of range out of range tracking alarm assert tracking alarm negate (b) phase condition (a) timing chart
fsan oc3 symmetric olt transceiver g983.3 classb- OAT1523S-OLT-V2-B-10 10 / document no: qps-0201-024 rev. draft 0.3 7. recommended interface circuit 08 sdatap 29 17 06 05 04 03 30 sdatan sclkp sclkn shut rsp 02,07,12,13,15, 19,22,25,27,28,31 brsp 32 01 16 18 21 26 rsn brsn poc svcc rvcc l v-pecl input cd td tf alm rdatap rdatan rclkp rclkn bvcc 23 24 14 20 10 11 09 +3.3 v gnd l v-pecl input lvttl output 1.6k 0.1uf 22uf 22uf 22uf 22uh 22uh 22uh svcc rvcc bvcc +3.3 v ztrm ztrm ztrm ztrm ztrm = lvttl input lvttl input 1.6k 1.6k +3.3 v 130 82 08 sdatap 29 17 06 05 04 03 30 sdatan sclkp sclkn shut rsp 02,07,12,13,15, 19,22,25,27,28,31 brsp 32 01 16 18 21 26 rsn brsn poc svcc rvcc l v-pecl input cd td tf alm rdatap rdatan rclkp rclkn bvcc 23 24 14 20 10 11 09 +3.3 v gnd l v-pecl input lvttl output 1.6k 0. 1 u f 0.1uf 0. 1 u f rvcc svcc bvcc 22uf 22uf 22uf 22uh 22uh 22uh svcc rvcc bvcc +3.3 v ztrm ztrm ztrm ztrm ztrm = lvttl input lvttl input 1.6k 1.6k +3.3 v 130 82
fsan oc3 symmetric olt transceiver g983.3 classb- OAT1523S-OLT-V2-B-10 11 / document no: qps-0201-024 rev. draft 0.3 8. precautions for handling the circuits of these modules operate at very small signal. in order to avoid the degradation of the optical sensitivity due to external noise, the bottom pattern of these modules on the pcb should be ground pattern with low impedance. do not mount/pattern device/circuits which generate high frequency noise close to the module. in order to operate the module stable against the power noise, install the power supply noise reduction circuits. the impedance between the power and ground pattern of the power circuit should be as low as possible . the elements around the module should be mounted close to the pins of the module. if optical power exceeding the absolute maximum ratings is fed to the module, the optical receiver may be damaged. set the optical input power appropriately when in use of these modules. 9. qualification and reliability t o help ensure high product reliability and customer satisfaction, oki i s committed to a n intensive quality program that starts in the design phase and proceeds through the manufacturing process. optical transceiver modules are qualified to oki internal standards using mil-std-883 test methods a n d procedures and using sample techniques consistent with telcordia requirements. this qualification program fully meets the intent of telcordia reliability practices gr-468-core. 10. laser safety all version s of transceiver are class 1 laser products fda compl i an t with 21 cfr 1040.10 and 1040.11 requirements. also, all versions are class 1 laser products pre iec 825-1.

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